An on-resistance of lateral metal-oxide-semiconductor field effect transistors (MOSFETs) has recently been reduced through an improvement of device structure and a device miniaturization. Furthermore, there have also been various efforts to reduce an on-resistance per unit area (Ron·A) with the device miniaturization. The on-resistance is one of indicators of resistance reduction.
One of factors effective in reducing a device area of a MOSFET is a layout of a source layer and a back gate layer in a source region. In one known example structure, in plan view from above the device, the source layer and the back gate layer are laid out in parallel to a gate electrode in a longitudinal direction of the device. In this layout, an area of the source region is made larger, and incurs the increase of overall device area. On the other hand, in another example structure, the source layer and the back gate layer are arranged in a line along the gate electrode alternately, or regularly in a certain ratio.
The length of the source region in the channel length direction can be reduced in the layout of the source layer and the back gate layer arranged in a channel width direction alternately or under a certain rule. That is, a device length can be reduced.
However, the source region is absent along the gate electrode in the back gate layer with a simple alternate arrangement of the source layer and the back gate layer. Hence, an effective gate width (an effective gate length in the channel width direction) decreases. The on-resistance (Ron·A) increases because the effective gate width decreases. Thus, even if the length in the channel length direction can be reduced, reduction of the on-resistance (Ron·A) cannot be achieved.
Thus, the source layer and the back gate layer are preferably intermittently-arranged in the channel width direction to reduce the length in the channel length direction. Furthermore, there is demand for a layout which can sufficiently ensure the effective gate width.